Power amplifier

ABSTRACT

An ultra-wideband power amplifier includes a preamplifier circuit and a post amplifier circuit. The preamplifier circuit includes a first DC blocking capacitor C 1 , a first decoupling capacitor C 2 , a second decoupling capacitor C 3 , a stabilizing resistor R in , a first AC blocking resistor RG 1 , a first input inductor L 1 , a second input inductor L 2 , an output inductor L 3 , a first input microstrip line MLIN 1 , a second input microstrip line MLIN 2 , an output microstrip line MLIN 3 , and a first transistor Q 1 . A first end of the first DC blocking capacitor C 1  acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C 1  is connected to the stabilizing resistor R in , the first input inductor L 1 , the first input microstrip line MLIN 1 , and a gate electrode of the first transistor Q 1  sequentially. One end of the first decoupling capacitor C 2  is grounded.

CROSS-REFERENCE TO RELATED APPLICATIONS

Pursuant to 35 U.S.C. § 119 and the Paris Convention Treaty, this application claims foreign priority to Chinese Patent Application No. 202210362457.1 filed Apr. 7, 2022, the contents of which, including any intervening amendments thereto, are incorporated herein by reference. Inquiries from the public to applicants or assignees concerning this document or the related applications should be directed to: Matthias Scholl P.C., Attn.: Dr. Matthias Scholl Esq., 245 First Street, 18th Floor, Cambridge, MA 02142.

BACKGROUND

The disclosure relates to the field of microwave integrated circuits, and more particularly, to an ultra-wideband power amplifier.

A power amplifier (PA) is a final stage core device of a transmission chain and is crucial to the operating distance of a wireless system. An ultra-wideband and high-linearity power amplifier is widely used in an integrated electronic system because of its comprehensive functions in radar, electronic countermeasures, communication data chain, etc.

Linearization techniques, such as load modulation and pre-distortion, increase the complexity of a power amplifier, and pose an adverse effect on the amplification effect. Narrow-band linearization techniques, such as Doherty, harmonic termination and harmonic injection, are unsuitable for use in an ultra-wideband power amplifier with multiple octave bands. Although a power backoff method increases the linearity, the amplification efficiency of the ultra-wideband power amplifier decreases. Thus, the ultra-wideband amplifiers are difficult to achieve both high efficiency and high linearity.

SUMMARY

To solve the aforesaid problems, the disclosure provides an ultra-wideband power amplifier having both high amplification efficiency and high linearity under low power backoff.

An ultra-wideband power amplifier comprises a preamplifier circuit and a post amplifier circuit; the preamplifier circuit comprises a first DC blocking capacitor C₁, a first decoupling capacitor C₂, a second decoupling capacitor C₃, a stabilizing resistor R_(in), a first AC blocking resistor RG₁, a first input inductor L₁, a second input inductor L₂, an output inductor L₃, a first input microstrip line MLIN₁, a second input microstrip line MLIN₂, an output microstrip line MLIN₃, and a first transistor Q₁; a first end of the first DC blocking capacitor C₁ acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C₁ is connected to the stabilizing resistor R_(in), the first input inductor L₁, the first input microstrip line MLIN₁, and a gate electrode of the first transistor Q₁ sequentially; a first end of the first decoupling capacitor C₂ is grounded, and a second end of the first decoupling capacitor C₂ is connected to the first AC blocking resistor RG₁, the second input inductor L₂, the second input microstrip line MLIN₂, and the gate electrode of the first transistor Q₁ sequentially; a junction of the first decoupling capacitor C₂ and the first AC blocking resistor RG₁ is connected to a gate supply voltage V_(gs1); a first end of the second decoupling capacitor C₃ is grounded, and a second end of the second decoupling capacitor C₃ is connected to the output inductor L₃, the output microstrip line MLIN₃, and a drain electrode of the first transistor Q₁ sequentially; a junction of the second decoupling capacitor C₃ and the output inductor L₃ is connected to a drain supply voltage V_(ds1); and a junction of the output inductor L₃ and the output microstrip line MLIN₃ acts as an output terminal of the preamplifier circuit;

A second DC blocking capacitor C₄ is disposed between the preamplifier circuit and the post amplifier circuit.

The post amplifier circuit comprising a first gate microstrip line MLIN₄, a second gate microstrip line MLIN₅, a third gate microstrip line MLIN₆, a fourth gate microstrip line MLIN₇, a drain inductor L₄, a first drain microstrip line MLIN₈, a second drain microstrip line MLIN₉, a second AC blocking resistor RG₂, a third decoupling capacitor C₅, a fourth decoupling capacitor C₆, a third DC blocking capacitor C₇, an AC blocking inductor L₅, a second transistor Q₂, a third transistor Q₃, and a fourth transistor Q₄; a first end of the gate microstrip line MLIN₄ acts as an input terminal of the post amplifier circuit, and a second end of the gate microstrip line MLIN₄ is connected to the second gate microstrip line MLIN₅, the third gate microstrip line MLIN₆, the fourth gate microstrip line MLIN₇, the second AC blocking resistor RG₂, and the third decoupling capacitor C₅ sequentially; and one end of the third decoupling capacitor C₅ is grounded; a junction of the second AC blocking resistor RG₂ and the third decoupling capacitor C₅ is connected to a gate supply voltage V_(gs2); a junction of first gate microstrip line MLIN₄ and the second gate microstrip line MLIN₅ is connected to a gate electrode of the second transistor Q₂; a junction of the second gate microstrip line MLIN₅ and the third gate microstrip line MLIN₆ is connected to a gate electrode of the third transistor Q₃; a junction of the third gate microstrip line MLIN₆ and the fourth gate microstrip line MLIN₇ is connected to a gate electrode of the fourth transistor Q₄; the drain inductor L₄ is disposed between drain electrodes of the second transistor Q₂ and the third transistor Q₃; the first drain microstrip line MLIN₈ is disposed between drain electrodes of the third transistor Q₃ and the fourth transistor Q₄; a junction of the first drain microstrip line MLIN₈ and the fourth transistor Q₄ is connected to a first end of the second drain microstrip line MLIN₉; a second end of the second drain microstrip line MLIN₉ is connected to first ends of the fourth decoupling capacitor C₆, the AC blocking inductor L₅, and the third DC blocking capacitor C₇; a second end of the fourth decoupling capacitor C₆ is grounded; a second end of the AC blocking inductor L₅ is connected to a voltage source V_(ds2); and a second end of the third DC blocking capacitor C₇ acts as an output terminal of the post amplifier circuit.

The ultra-wideband power amplifier comprises a preamplifier circuit and a post amplifier circuit. The ultra-wideband pre-amplifier circuit amplifies the input signal and can adjust the gate voltage. The circuit further amplifies the output signal of the previous stage. By matching a single transistor with a traveling wave structure, and then matching it with a multi-stage traveling wave structure, high linearity can be achieved and high efficiency can be maintained under low output power back-off, which solves the problems of linearity and efficiency of ultra-wideband power amplifiers.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an ultra-wideband power amplifier according to Example 1 of the disclosure;

FIG. 2 is a schematic diagram of an ultra-wideband power amplifier according to Comparison example 1 of the disclosure;

FIG. 3 is a graph of a simulation result obtained in accordance with Example 1 of the disclosure;

FIG. 4 is a comparison graph of simulation results obtained in accordance with Example 1 and Comparison example 1 of the disclosure; and

FIG. 5 is a comparison graph of simulation results obtained in accordance with Example 1 and Comparison example 1 of the disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

To further illustrate, embodiments detailing an ultra-wideband power amplifier are described below. It should be noted that the following embodiments are intended to describe and not to limit the disclosure.

Example 1

An ultra-wideband power amplifier comprises a power supply, a preamplifier circuit, a second DC blocking capacitor C₄, and a post amplifier circuit; the preamplifier circuit comprises a first DC blocking capacitor C₁, a first decoupling capacitor C₂, a second decoupling capacitor C₃, a stabilizing resistor R_(in), a first AC blocking resistor RG₁, a first input inductor L₁, a second input inductor L₂, an output inductor L₃, a first input microstrip line MLIN₁, a second input microstrip line MLIN₂, an output microstrip line MLIN₃, and a first transistor Q₁; the post amplifier circuit comprises a first gate microstrip line MLIN₄ and a multi-stage traveling-wave amplifier circuit; the multi-stage traveling-wave amplifier circuit comprises a second gate microstrip line MLIN₅, a third gate microstrip line MLIN₆, a fourth gate microstrip line MLIN₇, a drain inductor L₄, a first drain microstrip line MLIN₈, a second drain microstrip line MLIN₉, a second AC blocking resistor RG₂, a third decoupling capacitor C₅, a fourth decoupling capacitor C₆, a third DC blocking capacitor C₇, an AC blocking inductor L₅, a second transistor Q₂, a third transistor Q₃, and a fourth transistor Q₄; the first DC blocking capacitor C₁, the first decoupling capacitor C₂, the stabilizing resistor R_(in), the second AC blocking resistor RG₂, the first input microstrip line MLIN₁, and the second input microstrip line MLIN₂ are used to match a first impedance at an input terminal of the first transistor Q₁; the output microstrip line MLIN₃ is used to match a second impedance at an output terminal of the first transistor Q₁; and the preamplifier circuit is connected to the second DC blocking capacitor C₄, the first gate microstrip line MLIN₄, and the multi-stage traveling-wave amplifier circuit sequentially.

Simulation results of the ultra-wideband power amplifier show that a working frequency is 0.03-2.5 GHz, an output frequency is greater than 41 dBm, a power-added efficiency (PAE) is greater than 47%, a gain is greater than 15 dB; and the ultra-wideband power amplifier further comprises a signal source Z_(s) and a load Z_(L).

FIG. 1 is a schematic diagram of the ultra-band power amplifier of the disclosure. A radio frequency (RF) signal is transmitted to the preamplifier circuit for amplification; and the size of the first transistor Q₁ is small for better impedance matching and ultra-wideband amplification with flat gain.

The RF signal is transmitted from the preamplifier circuit to the post amplifier circuit via the second DC blocking capacitor C₄; the post amplifier circuit comprises a distributed amplifier topology; the first gate microstrip line MLIN₄ acts as an input terminal of the post amplifier circuit and adjusts an output impedance of the first transistor Q₁; the sizes of the second transistor Q₂, the third transistor Q₃, and the fourth transistor Q₄ are different for achieving an optimal power and an improved efficiency of impedance matching; and the drain inductor L₄ has a high inductance for better impendence matching.

Inductance and resistance are used to match an impedance at an input terminal of the preamplifier circuit so that an excellent standing wave is formed; and the preamplifier circuit is used in conjunction with the post amplifier to form a desired reverse isolation.

The first DC blocking capacitor C₁, second DC blocking capacitor C₄, and the third DC blocking capacitor C₇ are high-capacity off-chip capacitors for blocking a low-frequency DC signal; and the output inductor L₃ and AC blocking inductor L₅ are high-capacity off-chip inductors for preventing a loss of a low-frequency signal.

Multiple nonlinear components in the transistor are superpositioned, resulting in a sweet spot in a 3^(rd) order intermodulation distortion at a critical input power. Specifically, as the input power varies, the level of the 3^(rd) order intermodulation distortion is lowered to a minimum value, at which the corresponding input power is defined as the sweet spot. The preamplifier circuit is configured to send the output signal to the post amplifier circuit. The signal source is configured to generate a fundamental signal and transmit it to the preamplifier circuit. The preamplifier circuit outputs a plurality of signals that comprises a plurality of frequency components caused by a nonlinear effect; fundamental frequency components are nonlinear and generates 5^(th) and higher order frequency components; 3^(rd) order frequency components in the preamplifier circuit are produced by nonlinearity of the fundamental frequency components and by the 5^(th) and higher order frequency components; the plurality of frequency components, which have different amplitudes and phases, are transmitted to the post amplifier circuit; a plurality of more complex frequency components are produced due to a non-linear superposition of the plurality of frequency components; 3^(rd) order frequency components in the post amplifier circuit comprises the 3^(rd) order frequency components which are transmitted from the preamplifier circuit, amplified from the 3^(rd) order frequency components in the preamplifier circuit, and generated by 1^(st), 2^(nd), 5^(rd) and higher other order frequency components.

A gate supply voltage across the preamplifier circuit is adjusted to produce a plurality of non-linear frequency components having different amplitudes and phases; the plurality of non-linear frequency components is transmitted to the post amplifier circuit and results in different non-linear effects; the non-linear effects include the fact that the value for the sweet spot varies with the gate supply voltage across the preamplifier circuit; that is, the gate supply voltage is adjusted to produce different sweet spots; at each of the different sweet spots, the level of the 3^(rd) order intermodulation distortion is lowered to a minimum value, and a 3^(rd) order output intercept point (OIP3) has a maximum value; so the gate supply voltage is adjusted to make the plurality of sweet spot has a value close to a saturation output power, thus achieving a high-linearity and high-efficiency amplifier at a low back-off output power level. The power back-off method is also suitable for harmonic tuning.

The preamplifier circuit comprises a stabilizing resistor R_(in), a first AC blocking resistor RG₁, a first input inductor L₁, a second input inductor L₂, a first input microstrip line MLIN₁, a second input microstrip line MLIN₂, an output microstrip line MLIN₃, a first DC blocking capacitor C₁, a first decoupling capacitor C₂, a second decoupling capacitor C₃, a gate supply voltage V_(gs1), a drain supply voltage V_(ds1), and a first transistor Q₁; a first end of the first DC blocking capacitor C₁ is connected to the stabilizing resistor R_(in); and a second end of the first DC blocking capacitor C₁ is connected to the signal source Z_(s).

The power amplifier further comprises a second DC blocking capacitor C₄ disposed between the preamplifier circuit and the post amplifier circuit.

The post amplifier circuit comprises a first gate microstrip line MLIN₄, a second gate microstrip line MLIN₅, a third gate microstrip line MLIN₆, a fourth gate microstrip line MLIN₇, a drain inductor L₄, a first drain microstrip line MLIN₈, a second drain microstrip line MLIN₉, a second AC blocking resistor RG₂, a third decoupling capacitor C₅, and a fourth decoupling capacitor C₆, a third DC blocking capacitor C₇, an AC blocking inductor L₅, a second transistor Q₂, a third transistor Q₃, a fourth transistor Q₄, a gate supply voltage V_(gs2), and a drain supply voltage Vasa, a first end of the third DC blocking capacitor C₇ is connected to the second drain microstrip line MLIN₉; and a second end of the third DC blocking capacitor C₇ is connected to the load Z_(L).

The transistor comprises a source electrode that is grounded.

Comparison Example 1

A second example of the ultra-wideband power amplifier is illustrated in FIG. 2 . It is similar to the example described in Example 1, except for the following difference: the ultra-wideband power amplifier comprises a distributed amplifier topology instead of the preamplifier circuit. Simulation results of the ultra-wideband power amplifier in FIG. 2 show that a working frequency is 0.03-2.5 GHz, an output power is greater than 40 dBm, a gain is greater than 10 dB, and a power-added efficiency is greater than 48%.

FIG. 1 is a graph illustrating a simulation result of a position of a sweet spot in a 3^(rd) order intermodulation distortion at 12.00 MHz (with a frequency interval of 1 MHz) according to Example 3 of the disclosure.

FIGS. 4-5 are comparison graphs of simulation results obtained in accordance with Example 1 and Comparison example 1.

FIG. 4 is a comparison graph of IM3 and corresponding PAE at a minimum value of IM3 at 1200 MHz (with a frequency interval of 1 MHz) according to Example 1 and Comparison example 1. In Example 1, the output power back-off 1.4 dB, resulting in IM3 of −45 dBc and the corresponding PAE of 41%; and in Comparison example 1, the output power back-off 5 dB, resulting in IM3 of −35 dBc and the corresponding PAE of 38.3%.

FIG. 5 is a comparison graph of IM3 and corresponding PAE at a maximum value of IM3 at 2500 MHz (with a frequency interval of 1 MHz) according to Example 1 and Comparison example 1. In Example 1, the output power back-off 1.6 dB, resulting in IM3 of −46 dBc and the corresponding PAE of 38.5%; in Comparison example 1, the output power back-off 5 dB, resulting in IM3 of −41 dBc and the corresponding PAE of 31.6%.

In the disclosure, the pre-amplifier circuit comprises a single transistor matched amplifier and is matched with the multi-stage traveling wave amplifier of the post-stage; and the transistors are properly biased to improve linearity and efficiency of an ultra-wideband power amplifier.

It will be obvious to those skilled in the art that changes and modifications may be made, and therefore, the aim in the appended claims is to cover all such changes and modifications. 

What is claimed is:
 1. A power amplifier, comprising: 1) a preamplifier circuit, the preamplifier circuit comprising a first DC blocking capacitor C₁, a first decoupling capacitor C₂, a second decoupling capacitor C₃, a stabilizing resistor Rill, a first AC blocking resistor RG₁, a first input inductor L₁, a second input inductor L₂, an output inductor L₃, a first input microstrip line MLIN₁, a second input microstrip line MLIN₂, an output microstrip line MLIN₃, and a first transistor Q₁; and 2) a post amplifier circuit, the post amplifier circuit comprising a first gate microstrip line MLIN₄, a second gate microstrip line MLIN₅, a third gate microstrip line MLIN₆, a fourth gate microstrip line MLIN₇, a drain inductor L₄, a first drain microstrip line MLIN₈, a second drain microstrip line MLIN₉, a second AC blocking resistor RG₂, a third decoupling capacitor C₅, a fourth decoupling capacitor C₆, a third DC blocking capacitor C₇, an AC blocking inductor L₅, a second transistor Q₂, a third transistor Q₃, and a fourth transistor Q₄; wherein: a first end of the first DC blocking capacitor C₁ acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C₁ is connected to the stabilizing resistor R_(in), the first input inductor L₁, the first input microstrip line MLIN₁, and a gate electrode of the first transistor Q₁ sequentially; a first end of the first decoupling capacitor C₂ is grounded, and a second end of the first decoupling capacitor C₂ is connected to the first AC blocking resistor RG₁, the second input inductor L₂, the second input microstrip line MLIN₂, and the gate electrode of the first transistor Q₁ sequentially; a junction of the first decoupling capacitor C₂ and the first AC blocking resistor RG₁ is connected to a gate supply voltage V_(gs1); a first end of the second decoupling capacitor C₃ is grounded, and a second end of the second decoupling capacitor C₃ is connected to the output inductor L₃, the output microstrip line MLIN₃, and a drain electrode of the first transistor Q₁; a junction of the second decoupling capacitor C₃ and the output inductor L₃ is connected to a drain supply voltage V_(ds1); and a junction of the output inductor L₃ and the output microstrip line MLIN₃ acts as an output terminal of the preamplifier circuit; a second DC blocking capacitor C₄ is disposed between the preamplifier circuit and the post amplifier circuit; a first end of the first gate microstrip line MLIN₄ acts as an input terminal of the post amplifier circuit, and a second end of the first gate microstrip line MLIN₄ is connected to the second gate microstrip line MLIN₅, the third gate microstrip line MLIN₆, the fourth gate microstrip line MLIN₇, the second AC blocking resistor RG₂, and the third decoupling capacitor C₅ sequentially; and one end of the third decoupling capacitor C₅ is grounded; a junction of the second AC blocking resistor RG₂ and the third decoupling capacitor C₅ is connected to a gate supply voltage V_(gs2); a junction of first gate microstrip line MLIN₄ and the second gate microstrip line MLIN₅ is connected to a gate electrode of the second transistor Q₂; a junction of the second gate microstrip line MLIN₅ and the third gate microstrip line MLIN₆ is connected to a gate electrode of the third transistor Q₃; a junction of the third gate microstrip line MLIN₆ and the fourth gate microstrip line MLIN₇ is connected to a gate electrode of the fourth transistor Q₄; the drain inductor L₄ is disposed between drain electrodes of the second transistor Q₂ and the third transistor Q₃; the first drain microstrip line MLIN₈ is disposed between drain electrodes of the third transistor Q₃ and the fourth transistor Q₄; and a junction of the first drain microstrip line MLIN₈ and the fourth transistor Q₄ is connected to a first end of the second drain microstrip line MLIN₉; a second end of the second drain microstrip line MLIN₉ is connected to first ends of the fourth decoupling capacitor C₆, the AC blocking inductor L₅, and the third DC blocking capacitor C₇; a second end of the fourth decoupling capacitor C₆ is grounded; a second end of the AC blocking inductor L₅ is connected to a voltage source V_(ds2); and a second end of the third DC blocking capacitor C₇ acts as an output terminal of the post amplifier circuit. 